1. Field of the Invention
This invention is in the field of Static Random Access Memories ("SRAM"). Specifically, it relates to a technique for coupling a single sense amplifier to the memory cells on both sides of the memory array without incurring capacitance penalties.
2. Description of the Relevant Art
SRAM memories are well known. Such memories comprise an array of memory cells and associated addressing and detection peripheral circuits. Although the size of the array is arbitrary, using current fabrication techniques, a million or more memory cells can be formed on a single chip.
One such memory cell is shown in FIG. 1. Transistors T.sub.1, T.sub.2, T.sub.3, and T.sub.4 form a bistable cross-coupled flip-flop circuit, and transistors T.sub.5 through T.sub.8 form the gating network through which the interior nodes A and B of the flip-flop circuit are coupled to the One-bit line and the Zero-bit lines. Transistors T.sub.5 and T.sub.6 form an AND gate, as do transistors T.sub.7 and T.sub.8. For a random access memory, X and Y address signals are applied for coincident selection of the appropriate memory cell. A linear-selection scheme can also be used, in which case transistors T.sub.6 and T.sub.8 are omitted and the X address line represents the word line.
In a quiescent state both the X and Y address lines are at ground potential, isolating the memory flip-flop from both bit lines. If T.sub.2 is assumed to be ON, and T.sub.1 off, node A is at V.sub.dd and node B at 0 V. To read the cell, both address lines are pulsed (negative for P-channel MOS devices), which turns on transistors T.sub.5 through T.sub.8. Current will then flow into the One-bit line, which is kept at V.sub.dd by transistors T.sub.7 and T.sub.8 and transistor T.sub.2, which is ON. Little or no current flows through the Zero-bit line, which is also kept at V.sub.dd as transistor T.sub.1 is off. The state of the memory cell is thus determined by detecting on which bit line the sense current flows.
As SRAMs comprise so many essentially identical elements, it is convenient and known to arrange the individual memory cells symmetrically in the integrated circuit. FIG. 2 shows one common pattern. In known fashion, address decoding allows only one cell to be written or read at a given time. The output from that particular cell appears on the Zero- and One-bit lines.
In very large SRAM memories, more efficient use of the integrated circuit's area is achieved by arranging the memory cells in large groups, with the sensing circuitry needed to read the Zero- and One-bit sense lines being placed between the blocks of the cells. One such arrangement is shown in FIG. 3. Each group of memory cells is essentially identical, containing P rows and Q columns of memory cells. Between each pair of groups (12/14, 16/18) is a central area, herein regions 19 and 21, which contains the sensing circuitry for the memory cells on either side of it.
Differential sense amplifiers (`sense amplifiers`) are used to read the contents of the individual memory cells. The construction and operation of such amplifiers is known. It is also known to take advantage of the symmetrical arrangement of memory cells used in SRAM memories as shown in FIG. 3 to use a single group of sense amplifiers to read the output signals from memory cells in the blocks to both the left and right side of the central sensing circuitry.
In FIG. 2 the memory cells are designated by a block with a dashed number inside it indicative of the cell location. Thus, cell 1-2 is in row 1, column 2. As shown in FIG. 2, the output lines from the memory cells, the Zero- and One-bit lines, are brought out of the array to the sense amplifier (not shown). Each of the rows in a block of the array is connected to the same sense amplifier, the output of which indicates whether the memory cell in the selected row and column contains a 0 or 1. The buses from both the right and left side blocks are coupled together and in turn connected to the same sense amplifier in the central area. The buses and sense amplifiers are all known technology.
Although known arrangements have successfully reduced the area of the integrated circuit which must be devoted to sensing the contents of the memory cells, they have at least one major operational difficulty. The long buses which are needed to couple the memory cells on either side of the sensing circuitry to the sensing circuitry itself have large undesirable capacitances against which the signal generated by the memory cell must drive. This causes a large, undesirable power drain, and also slows the operation of the memory.
Consequently, there is a need for a sensing circuit which can receive signals from memory cells coupled through long buses to the sensing circuitry without adding unnecessary capacitance to the circuit.